In the manufacturing of electronic devices, the ever increasing device density places heavy demands on requirements in the packaging or interconnecting techniques of such highly dense devices. The fabrication of such electronic devices typically involves some form of substrate level packaging. The substrate level packaging may include forming vias and similar structures to provide internal and external device connections, for example input/output (I/O) connectivity. The formation of vias may involve the use of a polymer material having dielectric properties and stress buffering capabilities. However, the inventors have observed that as via sizes scale down in size, the polymer via openings cannot be reliably formed in the polymer material.
Thus, the inventors have developed improved techniques to form vias in polymer materials.